1. Technical Field
The present invention relates to semiconductor devices and semiconductor device packages, and more specifically, to a bonding pad array of a semiconductor device and a semiconductor device package including the same.
2. Description of the Related Art
Integrated circuit (IC) packaging technology in the semiconductor industry continues to develop in order to meet the demand for scaling down of size and improved mounting reliability. For example, demand for miniaturization has accelerated technology development of packages close to the size of a semiconductor chip. Also, demand for greater mounting reliability has driven development in packaging technology that can improve the efficiency of the mounting process, and mechanical and electrical reliability after the mounting process.
Also, various technologies for producing high capacity semiconductor products are being researched and developed, as miniaturization and a high degree of integration continue to be required. Methods for providing high capacity semiconductor products include increasing the storage capacity of the memory chip, i.e., a high degree of integration of the memory chip. Such high integration of the memory chip can be realized by integrating a higher number of memory cells in the limited space of a semiconductor chip.
However developing such high integration of the memory chip takes significant time and requires advanced technology, such as process precision and extra-fine line widths. Accordingly, a method of vertically stacking a plurality of semiconductor chips or semiconductor device packages has been proposed. Such a stacking method produces an advantage in mounting density and in mounting area use efficiency as well as an increase in memory storage capacity. Therefore research and development in stack-structured semiconductor device packages continues.
FIG. 1A and FIG. 1B are a sectional view and a top plan view of a conventional semiconductor device package, respectively.
Referring to FIGS. 1A and 1B, a semiconductor device package includes first and second semiconductor devices 10a and 10b and a wiring substrate 20.
The first and second semiconductor devices 10a and 10b include a control pin bonding pad 12ac and 12bc, at least one electrical die sorting (EDS) bonding pad 12ae and 12be, and a plurality of signal bonding pads 12as and 12bs, the bonding pads disposed on the respective active surfaces of the first and second semiconductor devices 10a and 10b. Each of the bonding pads is configured to be connected to penetrating electrodes which penetrate the first and second semiconductor devices 10a and 10b. 
The EDS bonding pad 12ae of the first semiconductor device 10a and the EDS bonding pad 12be of the second semiconductor device 10b are electrically connected. The signal bonding pads 12as of the first semiconductor device 10a and the signal bonding pads 12bs of the second semiconductor device 10b are electrically connected. Such electrical connections are made by connection electrodes 16 included in an adhesive material layer 15 provided between the first and second semiconductor devices 10a and 10b. The control pin bonding pad 12ac of the first semiconductor device 10a and the control pin bonding pad 12bc of the second semiconductor device 10b are not electrically connected.
The wiring substrate 20 may include a system board such as a printed circuit board (PCB). The wiring substrate 20 having a core material 22 as the body, includes an upper surface insulation layer pattern 24u including upper bonding electrodes 26u, and a lower surface insulation layer pattern 24l opposite of the upper surface insulation layer pattern 24u, the lower surface insulation layer pattern 24l including lower bonding electrodes 26l. 
The wiring substrate 20 has the upper bonding electrodes 26u which correspond to the bonding pads 12ac, 12ae and 12as of the first semiconductor device 10a, the upper bonding electrodes 26u disposed on the upper surface of the wiring substrate 20. The upper bonding electrodes 26u are electrically connected to their corresponding bonding pads 12ac, 12ae and 12as of the first semiconductor device 10a. The first and second semiconductor devices 10a and 10b are vertically stacked and mounted on the wiring substrate 20 with a mounting adhesive material layer (not shown).
The wiring substrate 20 has the lower bonding electrodes 26l for forming solder balls 28s on the lower surface. The solder balls 28s provided on the lower surface of the wiring substrate 20 are connected to internal interconnections (bent solid lines) to provide electrical connections between the stacked first and second semiconductor devices 10a and 10b and external circuits. Signal solder balls A0, A1 and A2 are connected to the signal bonding pads 12as of the first semiconductor device 10s by the internal interconnections of the wiring substrate 20. Control solder balls ct10 and ct11 are respectively connected to the control pin bonding pad 12ac and the EDS bonding pad 12ae of the first semiconductor device 10a by the internal interconnections of the wiring substrate 20.
The semiconductor device package including the stacked first and second semiconductor devices 10a and 10b controls each of the semiconductor devices 10a and 10b so as to selectively operate the semiconductor devices 10a and 10b. While the first semiconductor device 10a is able to receive an operation signal directly through the control pin bonding pad 12ae, an additional connection line 13sl connecting the control pin bonding pad 12bc and the EDS bonding pad 12be is required in order for the second semiconductor device 10b to be able to receive an operation signal.
A semiconductor device package having the above-explained structure can control the operation of stacked semiconductor devices by using an electrical die sorting bonding pad. However there is a large difference between the physical lengths of the interconnections used as the paths receiving an operation signal in the stacked semiconductor devices. Thus, there is a problem of signal delay that may occur because of the difference in physical lengths of the interconnections used in the stacked semiconductor devices.